SMRAM Size Overhead

PE image

In order to protect the PE code and data sections, we must set the PE image section alignment to be 4K.

In EDK II, the default PE image alignment is 0x20 bytes. Assuming one PE image has 3 sections (1 header, 1 code section, 1 data section), average overhead for one PE image is (4K * 3) / 2 = 6K.

If a platform has n SMM images, the average of the overhead is 6K * n.

Page Table

In order to protect the page table itself, we must use the static page table instead of the dynamic on-demand page table.

The size of the dynamic paging is fixed. We need 6 fixed pages (24K) and 8 on-demand pages (32K). The total size of the page table is 56K in this case.

The size of the static page table depends upon 2 things: 1) 1G paging capability, 2) max supported address bit. A rough estimation is below:

1. If 1G paging is supported,
2. 32 bit addressing need (1+1+4) pages = 24K. (still use 2M paging for below 4G memory)
3. 39 bit addressing need (1+1+4) pages = 24K.
4. 48 bit addressing need (1+512) pages = 2M.
5. If 1G paging is not supported, 2M paging is used.
6. 32 bit addressing need (1+1+4) pages = 24K.
7. 39 bit addressing need (1+1+512) pages = 2M.
8. 48 bit addressing need (1+512+512512) pages = 1G. < - This seems __***not** acceptable.

The maximum address bit is determined by the (CPU_HOB) if it is present, or the physical address bit returned by the CPUID instruction if the CPU_HOB is not present. (https:\/\/github.com\/tianocore\/edk2\/blob\/master\/UefiCpuPkg\/PiSmmCpuDxeSmm\/X64\/PageTbl.c, CalculateMaximumSupportAddress()) A platform may set the CPU_HOB based upon the addressing capability of the memory controller or the CPU.